1. Field of the Invention
This invention relates to integrated circuit testing and, more particularly, to built-in self-testing of embedded memories.
2. Description of the Related Art
During development testing of an integrated circuit (IC) that includes a memory array, it is typically important to fully test the memory across various manufacturing process changes. For example, when a device is first manufactured, typically referred to as first silicon, the wafer fabrication process may need to be adjusted to accommodate all processing corners. For devices with memory arrays, a bitmap of the array may be created during memory testing to ensure or establish the various process corners of the process. A bitmap is a mapping of each memory location in a particular memory array. The bitmap may show the pass/fail status of each location, or it may show other data. Generally speaking, a bitmap may be created by test software running on a device test system using pass/fail information, for example, sent to the tester from the device under test during testing. There are various techniques to generate such a bitmap.
However, depending on how the memory array pass/fail information is provided back to the tester, bitmapping large arrays can be test time intensive. For example, in one technique each memory location may be read, and the data and a pass fail indication may be sent to the tester after each read (referred to as normal mode bitmapping). This technique can be very time consuming.
In another technique, known as nth fail mode, each location is read and after some predetermined number (n) of failures the clock is stopped and the data for the current failed location is sent to the tester. Using this technique, testing can be done at-speed. In some cases nth fail mode testing may be done as much as 60 times as fast as normal mode bitmapping. However, there can be significant drawbacks to nth fail mode bitmapping, particularly for high frequency devices. For example, stopping on the nth fail to output the data requires locking of the compare data in the same cycle that the error is detected. To do so in high frequency devices can be expensive in terms of additional hardware overhead (e.g., use of additional “shadow flops” or high power flops) to stop the clock. Alternatively, to reduce the hardware complexity, there are some hardware simplifications such as partial locking, that may be used. But to do so can compromise the bitmap data quality.